Stress impacts the performance of semiconductor devices by altering the band structure of the semiconductor material, and consequently, the mobility of carriers. This effect is prominent in many semiconductor devices, e.g., metal-oxide-semiconductor field effect transistor (MOSFET) devices. For example, minority carriers in the body, e.g., hole mobility of a p-type MOSFET, formed on a silicon substrate increases under a uniaxial compressive stress in the direction of the channel, i.e., along a line connecting the source and the drain, thereby impacting transconductance of a MOSFET. The electron mobility of an n-type MOSFET formed on a silicon substrate increases under a tensile stress in the direction of the channel. The change in the mobility of minority carriers depends on the type and direction of stress as well as the semiconductor substrate material.
As a physical quantity, stress is defined at every point in a semiconductor device as a three-dimensional tensor, thus forming a tensor field within a semiconductor structure. Since the stress is generated by physical structures, variations in the arrangement in the physical structures around the semiconductor device results in variations in the stress. Thus, accurate modeling of semiconductor devices requires modeling of the effects of stress on semiconductor devices.
Methods of modeling stress in semiconductor devices for device modeling and circuit simulation purposes are known.
As stress effects in silicon processing cause displacements in the silicon lattice in intermediate stages of silicon processing, these displacements may cause overlay error between mask layers.
For example, during the manufacture of embedded DRAM layouts, there can be overlay errors between DT and RX shapes (where DT is a deep trench and RX recessed oxide), induced during the annealing of deep trench structures. Signature of overlay errors exhibit strong correlation to DT pattern density gradients.
The displacement of DT shapes was related to stress and it is recognized that stress can be the source of systematic, within-field overlay error.
Similar issues have been observed in fin-FET eDRAM devices. For example, in a fin-FET eDRAM, overlay errors between trenches and fins have been observed and the errors correlate highly to DT density gradients. The observed overlay error did not meet the required tolerances.
Currently, as an annealing step may be a cause of induced stress, one possible solution is to reduce stress. Process modifications were looked at as a means to reduce stress, but eliminating the stress completely may not be possible. Another method to address the problem is to try to improve the design uniformity through the reticle field (via dummy fill, design rules, etc. . . . ). This is a commonly applied technique, but the inability to place DT (deep trenches) in some areas of logic and SRAM (under non-eDRAM devices) prevents this from being a completely successful mitigation technique.